Dr. Baumgart received his B.S. degree in physics from the University of Heidelberg, Germany, his M.S. degree in physics from Purdue University in Indiana, where he attended graduate school as a Fulbright Scholar, and his Ph.D. degree in semiconductor physics from the University of Stuttgart, Germany, while performing his Ph.D. research at the Max-Planck Institute of Solid State Research in Stuttgart. Following graduation he has held numerous R&D positions in the microelectronics industry.
He has worked at AT&T Bell Laboratories in Murray Hill, New Jersey, with the Electronic Materials Applications Research Department; at Royal Philips Electronics Briarcliff Research Laboratories in New York with their Microelectronic Devices Research Dept. and at Royal Philips Electronics Research Headquarters at the Natuurkundig Laboratorium at the High Tech Campus Eindhoven, the Netherlands; at Siemens Semiconductors and at IBM Microelectronics at the Advanced Semiconductor Technology Center (ASTC) in East Fishkill, New York; at Infineon Technologies in Richmond, Virginia, and at Motorola’s Advanced Products Research & Development Laboratories (APRDL) in Austin, Texas, where he specialized in CMOS logic platform development and high performance CMOS in Silicon-on-Insulator technology; and at HPL Technologies (Heuristic Physics Laboratories) Test Chip Division in Austin, Texas. Dr. Baumgart has conducted research and worked in the areas of Silicon-on-Insulator (SOI) Technology; Wafer Bonding Technology, FIPOS Technology (Full Isolation by Porous Oxidized Silicon), Laser-induced Zone Melt Recrystallization (ZMR) Technology, SIMOX Technology, Rapid Thermal Annealing; Lateral Double Diffused LDMOS High Voltage Devices and Power ICs in SOI Technology, Development of LDMOS High Voltage Transistor Process with raised drain–source regions and ultra thinned drift region in SOI Technology utilizing the RESURF(Reduced Surface Electric Field ) Principle; Integrated Circuit Semiconductor Fabrication for Logic and Memory applications; in 64Mb & 256Mb DRAM memory manufacturing the development of deep Trench Capacitor Front End of Line (FEOL) module, Process Capability Benchmarking, Statistical Process Control, Failure Mode and Effects (FMEA) Analysis, and in 130nm & 90nm CMOS Logic Platforms, process integration of BEOL related technology issues in dual inlaid Cu backend metallization; and low-k Interconnect Dielectrics, Failure Analysis of random and systematic yield detractors, Yield Enhancement, Technology Development TDSRAM and TDROM Test Chip Analysis Methodology for the 90nm and 65nm Logic Technology node, Development of BEOL Test Chip Library.
In his research areas he has authored and co-authored 55 papers, he has published and edited 8 Electrochemical Society Conference Proceedings Volumes, he has delivered 27 conference presentations including numerous invited talks, and has three U.S. Patents and 15 Patent Disclosures. In 2002 he received the Motorola Award “Most Significant Contribution to 2002 Defect Density Goals“ for the MOS-13 HIP7 Contact Process Recovery Team, in 2001 he received the Infineon Technologies Special Recognition Award for Leadership of the FMEA Team and FMEA Fab Cluster Standardization, in 1989 he received the Special Merit Award Philips Research, in 1985 the Special Merit Award Philips Research and in 1984 he received the President’s Making a Difference Award Philips Research. He is serving on the Executive Committee of the Electronics Division of The Electrochemical Society.
In the fall of 2005 Dr. Baumgart joined the faculty of Old Dominion University in the Department of Electrical and Computer Engineering in Norfolk, Virginia. His current research interests include Nanotechnology, Microelectronics Fabrication, Semiconductor Device Processing, Gate Stack Engineering, High-k Dielectrics for advanced gate stack integration in CMOS logic and DRAM capacitor applications, Atomic Layer Deposition (ALD) Technology of electronic thin film materials, Silicon-on-Insulator (SOI) Technology and Germanium-on-Insulator (GeOI) Technology for high performance devices.